The Ten64 board supports DDR4 SODIMM's with (and without) ECC running at 2100MT/sec (faster sticks are generally backwards-compatible).
The LS1088 DDR controller is generally designed for embedded use cases, hence it requires data about the memory devices before hand to set up its timing and write levelling mechanisms.
Support for SO-DIMM's is based on the JEDEC PCB reference design (also called "Raw Card"). At the time of writing JEDEC has released designs A through to K, but only a few are used in practice (especially for speeds >=2666MT/s). Most reference designs have more than one version, as higher DDR4 speeds require tighter timing margins.
Generally Traverse stocks Innodisk brand memory, but we will implement support for other vendors and models on request.
List of tested SO-DIMM's:¶
|Manufacturer||Model||Size||ECC||Ref Design||Advertised Speed||Supported||Comments / Datasheet (if any)|
|Micron||MTA18ASF2G72HZ-2G6E1ZK||16GB||YES||G1||2666||YES||Also known as Crucial CT16G4TFD8266. Datasheet on micron.com (login required), previous model is ref card H not tested|
|Crucial||CT4G4SFS8266.C8FE||4GB||NO||A2||2666||YES||Crucial Website, does not have a corresponding Micron OEM version. SPD contains incorrect DQ byte mappings, fixed in firmware. (Tsk tsk Crucial!)|
Tip: The Ref card version can be found in the standard JEDEC model ID that is on the label of most cards, for example:
- Samsung M471A4G43MB1-CTD: PC4-2666V-S E1 -11
- Micron MTA18ASF2G72HZ-2G6E1ZK: PC4-2666V-T G1 -11
When BL2/TF is compiled in debug mode, the raw card parameter will be printed out at boot:
INFO: RCW BOOT SRC is QSPI INFO: RCW BOOT SRC is QSPI WARNING: Using I2C3 for DDR SPD INFO: platform clock 700000000 INFO: DDR PLL 2100000000 INFO: time base 11 ms INFO: Parse DIMM SPD(s) .... INFO: n_ranks 2 INFO: rank_density 0x400000000 INFO: capacity 0x800000000 INFO: die density 0x6 INFO: primary_sdram_width 64 INFO: ec_sdram_width 0 INFO: device_width 8 INFO: package_3ds 0 INFO: rc 0x24 (Raw card E1) INFO: rdimm 0 INFO: mirrored_dimm 1 INFO: n_row_addr 17 INFO: n_col_addr 10
Despite support for most reference designs being implemented, we have found quite a few memory modules ship with incorrect data in their EEPROM (SPD), requiring workarounds in our memory init code. If an unimplemented SO-DIMM fails to boot despite support for the reference design in BL2, we can usually determine the cause of the problem from the full (debug) boot log.
Adding support for new SO-DIMM's / raw cards¶
The following parameters are needed to support a SO-DIMM card:
- JEDEC raw card ID
- Clock adjust and base write level values (for the first byte lane)
- Write level values for the remaining byte lanes
The clock adjust and write level values are found via NXP's CodeWarrior QCVS DDR tool - which determines the most stable values by iteration on the actual hardware. In theory, you could try and determine these intuitively based on the DIMM net lengths - but we don't recommend this!
These are put into a table in the Trusted Firmware ddr_init.c.